Low power-state management and PSI#

L6756D

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Low power-state management and PSI#

PSI# is an active-low input that can be set by the CPU to allow the regulator to enter power-

saving mode to maximize the system efficiency when in light-load conditions. The controller

constantly monitors the PSI_A pin to define the PSI strategy, that is the action performed by

the controller when PSI# is asserted. According to Table 9, by programming different

voltages on PSI_A, it is possible to configure the device to work at one or two phases while

PSI# is asserted. The device can also be configured to take no action so phase number will

not change after PSI# assertion.

In case the phase number is changed, the device will disable one or more phases by setting

in HiZ the relative PWM and re-configuring the internal phase-shift to maintain the

interleaving. Furthermore, the internal current-sharing will be adjusted to consider the phase

number reduction. ENDRV will remain asserted.

When PSI# is de-asserted, the device will return to the original configuration.

Start-up is performed with all the configured phases enabled. In case of DVID transitions,

the device will use all the phases available to perform the transition coming back to the PSI

reduced number of phases after the transition has.

PSI Strategy is continuously monitored across PSI_A pin.

Caution:

When PSI_A is set for working at 2phases when PSI# is asserted, the IC will work as if

configured for 2phases so enabling only Phase1 and Phase3.

Table 9.

PSI strategy

Figure 12.

System efficiency enhancement by PSI#

PSI_A

PSI Strategy

PSI#/VR10

GND / Open

No strategy.

IC will work in VR11 mode

VR10

100 k

Ω to VREF

Phase number set to 2 while PSI# is asserted (only phase1

and Phase3 are active).

PSI#

to VREF

Phase number set to 1 while PSI# is asserted (only phase1

is active).