L6756D

System control loop compensation

31/36

Figure 15.

Control loop bode diagram and fine tuning

implementation. A zero at

ω

integrator minimizes the static error while placing the zero

ω

C resonance assures a simple -20 dB/dec shape of the gain.

In fact, considering the usual value for the output filter, the LC resonance results to be at

frequency lower than the above reported zero.

Compensation network can be simply designed placing

ω

over frequency

ω

9.1

Compensation network guidelines

The compensation network design assures to having system response according to the

cross-over frequency selected and to the output filter considered: it is anyway possible to

further fine-tune the compensation network modifying the bandwidth in order to get the best

response of the system as follow (See Figure 15):

–

–

–

system phase margin.

Having the fastest compensation network gives not the confidence to satisfy the

requirements of the load: the inductor still limits the maximum dI/dt that the system can

afford. In fact, when a load transient is applied, the best that the controller can do is to

dV/dt is then limited by the inductor charge / discharge time and by the output capacitance.

In particular, the most limiting transition corresponds to the load-removal since the inductor

appliance).

R

F

R

FB

ΔV

OSC

⋅

V

IN

----------------------------------

10

6

------

ω

T

L

NR

LL

ESR

+

()

⋅

-------------------------------------------

⋅⋅

⋅

=

C

F

C

O

L

⋅

R

F

--------------------

=