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L6756D 数据表(PDF) 33 Page - STMicroelectronics

部件名 L6756D
功能描述  2/3/4 phase buck controller for VR10, VR11 and VR11.1 processor applications
PDF  36 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

L6756D 数据表(HTML) 33 Page - STMicroelectronics

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L6756D
System control loop compensation
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Sensitivity of the load transient detector and the gain of the LTB ramp can be programmed in
order to control precisely both the undershoot and the ring-back.
Detector design. RLTB - CLTB is design according to the output voltage deviation dVOUT
which is desired the controller to be sensitive as follow:
Gain design. Through the LTBGAIN pin it is possible to modify the slope of the LTB
Ramp in order to modulate the entity of the LTB response once the LT has been
detected. In fact, the response depends on the board design and its parasites requiring
different actions from the controller.
Leaving the LTBGAIN pin floating, the maximum pulse-width is programmed. The slope
of the LTB ramp will be equal to 1/2 of the OSC ramp slope.
Connecting RLTBGAIN to GND, the LTB Ramp slope can be modified as follow:
Where ILTBGAIN is the current sunk from LTBGAIN pin and IOSC is the OSC current
(20
μA plus the current coming from the OSC pin).
LTB Technology® design tips.
Descries RLTB to increase the system sensitivity making the system sensitive to
smaller dVOUT.
Increase CLTB to increase the system sensitivity making the system sensitive to
higher dV/dt.
Increase RLTBGAIN to increase the width of the LTB pulse.
R
LTB
dV
OUT
25
μA
------------------
=
C
LTB
1
2
πNR
LTB
F
SW
⋅⋅
----------------------------------------------
=
LTBRamp
Slope
OSC
Slope
1
I
LTBGAIN
I
OSC
------------------------
+
⎝⎠
⎛⎞
=



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