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L6566ATR 数据表(PDF) 19 Page - STMicroelectronics |
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L6566ATR 数据表(HTML) 19 Page - STMicroelectronics |
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19 / 51 page ![]() L6566A Application information 19/51 With reference to the timing diagram of Figure 6, when power is first applied to the converter the voltage on the bulk capacitor (Vin) builds up and, at about 80 V, the HV generator is enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This current, minus the device’s consumption, charges the bypass capacitor connected from pin Vcc (5) to ground and makes its voltage rise almost linearly. Figure 6. Timing diagram: normal power-up and power-down sequences As the Vcc voltage reaches the start-up threshold (14 V typ.) the low-voltage chip starts operating and the HV generator is cut off by the Vcc_OK signal asserted high. The device is powered by the energy stored in the Vcc capacitor until the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. The residual consumption of this circuit is just the one on the 15 M Ω resistor ( ≈10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as compared to a standard start-up circuit made with external dropping resistors. At converter power-down the system will lose regulation as soon as the input voltage is so low that either peak current or maximum duty cycle limitation is tripped. Vcc will then drop and stop IC activity as it falls below the UVLO threshold (10 V typ.). The Vcc_OK signal is de-asserted as the Vcc voltage goes below a threshold Vccrestart located at about 5 V. The HV generator can now restart. However, if Vin < Vinstart, as illustrated in Figure 6, HV_EN is de-asserted too and the HV generator is disabled. This prevents converter’s restart attempts and ensures monotonic output voltage decay at power-down in systems where brownout protection (see the relevant section) is not used. The low restart threshold Vccrestart ensures that, during short circuits, the restart attempts of the device will have a very low repetition rate, as shown in the timing diagram of Figure 7 on page 20 , and that the converter will work safely with extremely low power throughput. Vcc (pin 5) GD (pin 4) HV_EN VccON VccOFF Vccrestart t t t t Vin VHVstart Icharge 0.85 mA t t Vcc_OK Power-on Power-off Normal operation regulation is lost here Vcc_PFC (pin 6) heavy load light load |
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