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L6566ATR 数据表(PDF) 34 Page - STMicroelectronics |
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L6566ATR 数据表(HTML) 34 Page - STMicroelectronics |
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34 / 51 page ![]() Application information L6566A 34/51 operating, so that the converter will work intermittently, which is very safe. In case of overload the system has a power capability lower than that at nominal load but the output current may be quite high and overstress the output rectifier. In case of FF operation the capability is almost unchanged and both short circuit and overload conditions are more critical to handle. The L6566A, regardless of the operating option selected, makes it easier to handle such conditions: the 2 V clamp on the SS pin is removed and a second internal current generator ISS2 = ISS1 /4 keeps on charging Css. As the voltage reaches 5 V the device is disabled, if it is allowed to reach 2 VBE over 5 V, the device will be latched off. In the former case the resulting behavior will be identical to that under short circuit illustrated in Figure 6 on page 19 ; in the latter case the result will be identical to that of Figure 20 on page 33. See Section 5.9: Latched disable function on page 32 for additional details. A diode, with the anode to the SS pin and the cathode connected to the VREF pin (10) is the simplest way to select either auto-restart mode or latch-mode behavior upon overcurrent. If the overload disappears before the Css voltage reaches 5 V the ISS2 generator will be turned off and the voltage gradually brought back down to 2 V. Refer to the Section 6: Application examples and ideas on page 44 section (Figure 7 on page 45) for additional hints. If latch-mode behavior is desired also for converter’s short circuit, make sure that the supply voltage of the device does not fall below the UVLO threshold before activating the latch. Figure 21 shows soft-start pin behavior under different operating conditions and with different settings (latch-mode or autorestart). Note: Unlike other PWM controllers provided with a soft-start pin, in the L6566A grounding the SS pin does not guarantee that the gate driver is disabled. Figure 21. Soft-start pin operation under different operating conditions and settings t Vcc (pin 5) SS (pin 14) t t COMP (pin 9) START-UP TEMPORARY OVERLOAD OVERLOAD t GD (pin 4) NORMAL OPERATION NORMAL OPERATION RESTART here the IC shuts down here the IC latches off Vcc falls below UVLO before latching off SHUTDOWN LATCHED AUTORESTART UVLO 2V 5V 5V+2Vbe t Vcc_PFC (pin 6) |
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