L6566ATR datasheet(30/51 Pages) STMICROELECTRONICS

30 / 51 page

Application information

L6566A

30/51

Equation 8

where Lp is the inductance of the primary winding. In case a constant maximum power

capability vs. the input voltage is not required, the VFF pin can be grounded, directly or

through a resistor (see Section 5.11: OVP block on page 35 ), hence fixing the overcurrent

setpoint at 1 V, or biased at a fixed voltage through a divider from VREF to get a lower

setpoint.

It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to ensure

a clean operation of the IC even in a noisy environment.

The pin is internally forced to ground during UVLO, after activating any latched protection

and when pin COMP is pulled below its low clamp voltage (see Section 5.5: PWM control

block on page 26

5.7

Hiccup-mode OCP

A third comparator senses the voltage on the current sense input and shuts down the device

if the voltage on the pin exceeds 1.5 V, a level well above that of the maximum overcurrent

setpoint (1 V). Such an anomalous condition is typically generated by either a short circuit of

the secondary rectifier or a shorted secondary winding or a hard-saturated flyback

transformer.

To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the

first time the comparator is tripped the protection circuit enters a “warning state”. If in the

next switching cycle the comparator is not tripped, a temporary disturbance is assumed and

the protection logic will be reset in its idle state; if the comparator will be tripped again a real

malfunction is assumed and the L6566A will be stopped. Depending on the time relationship

between the detected event and the oscillator, occasionally the device could stop after the

third detection.

This condition is latched as long as the device is supplied. While it is disabled, however, no

energy is coming from the self-supply circuit; hence the voltage on the Vcc capacitor will

decay and cross the UVLO threshold after some time, which clears the latch. The internal

start-up generator is still off, then the Vcc voltage still needs to go below its restart voltage

before the Vcc capacitor is charged again and the device restarted. Ultimately, this will result

in a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on

the power circuit. This special condition is illustrated in the timing diagram of Figure 18.

opt =

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