L6566ATR datasheet(36/51 Pages) STMICROELECTRONICS

36 / 51 page

Application information

L6566A

36/51

Figure 23.

OVP function: timing diagram

The ZCD pin will be connected to the auxiliary winding through a resistor divider RZ1, RZ2

(see Figure 8 on page 20). The divider ratio kOVP = RZ2 / (RZ1 + RZ2) will be chosen equal

to:

Equation 10

where VoutOVP is the output voltage value that is to activate the protection, Ns the turn

number of the secondary winding and Naux the turn number of the auxiliary winding. The

value of RZ1 will be such that the current sourced by the ZCD pin be within the rated

capability of the internal clamp:

Equation 11

where Vinmax is the maximum dc input voltage and Ns the turn number of the primary

winding. See Section 5.2: Zero current detection and triggering block; oscillator block on

page 21

for additional details.

To reduce sensitivity to noise and prevent the latch from being erroneously activated, first

the OVP comparator is active only for a small time window (typically, 0.5 µs) starting 2 µs

after MOSFET’s turn-off, to reject the voltage spike associated to the positive-going edges

of the voltage across the auxiliary winding Vaux; second, to stop the L6566A the OVP

comparator must be triggered for four consecutive switching cycles. A counter, which is

reset every time the OVP comparator is not triggered in one switching cycle, is provided to

this purpose.

(pin 4)

Vaux

STROBE

COUNTER

RESET

COUNTER

STATUS

ZCD

(pin 11)

2 µs

0.5 µs

OVP

FAULT

→11 →22 →00 →11 →22 →33 →4

NORMAL OPERATION

TEMPORARY DISTURBANCE

FEEDBACK LOOP FAILURE

COUT

Vcc_PFC

(pin 6)

Naux

Vout

OVP

OVP =

max

Vin

Naux

−

⋅

≥

L6566ATR 数据表(PDF) 36 Page - STMicroelectronics

L6566ATR 数据表(HTML) 36 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

数据表下载