HD6417618 datasheet(350/646 Pages) RENESAS

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Section 13 Compare Match Timer (CMT)

Rev. 6.00 Jun. 12, 2007 Page 318 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

value

R/W

Description

CKS1

CKS0

R/W

Clock Select 1 and 0

Select the clock to be input to CMCNT from four

internal clocks obtained by dividing the peripheral

operating clock (P

φ). When the STR bit in CMSTR is

set to 1, CMCNT starts counting on the clock selected

with bits CKS1 and CKS0.

00: P

φ/8

01: P

φ/32

10: P

φ/128

11: P

φ/512

Note: *

Only 0 can be written, to clear the flag.

13.2.3

Compare Match Counter (CMCNT)

CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with

bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts counting

using the selected clock.

When the value in CMCNT and the value in compare match constant register (CMCOR) match,

CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1.

CMCNT is initialized to H'0000 by a power-on reset and a transition to standby mode.

13.2.4

Compare Match Constant Register (CMCOR)

CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT.

CMCOR is initialized to H'FFFF by a power-on reset and is initialized to H'FFFF in standby

mode.

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