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HD6417618 数据表(PDF) 92 Page - Renesas Technology Corp

部件名 HD6417618
功能描述  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

HD6417618 数据表(HTML) 92 Page - Renesas Technology Corp

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Section 3 Cache
Rev. 6.00 Jun. 12, 2007 Page 60 of 610
REJ09B0131-0600
(1) Address array access
(a) Address specification
Read access
Write access
(b) Data specification (both read and write accesses)
(2) Data array access (both read and write accesses)
(a) Address specification
1111 0000
*--------*
W
Entry address
1111 0000
*--------*
W
Entry address
A
31 30 29
10
4 3
0
LRU
2
X
00
0
X
9
Tag address (28 to 10)
U V
1
31
24 23
4 3
0
1111 0001
*--------*
W
Entry address
1
2
L
(b) Data specification
31
0
Longword
[Legend]
*:
Don't care
X: 0 for read, don't care for write
0
00
28
*
0
0
31
24 23
4 3
0
1
2
31
24 23
12 11 10 9
(14*) (13*) (12*) (11*)
12 11 10 9
(14*) (13*) (12*) (11*)
12 11 10 9
(14*) (13*) (12*) (11*)
43
0
1
2
*
00
Note: * For the SH7618A.
Figure 3.4 Specifying Address and Data for Memory-Mapped Cache Access



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