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HD6417618 数据表(PDF) 83 Page - Renesas Technology Corp

部件名 HD6417618
功能描述  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

HD6417618 数据表(HTML) 83 Page - Renesas Technology Corp

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Section 3 Cache
Rev. 6.00 Jun. 12, 2007 Page 51 of 610
REJ09B0131-0600
3.1.2
Divided Areas and Cache
A 4-G byte address space is divided into five areas with the architecture of this LSI. The cache
access methods can be specified for each area. Table 3.2 lists the correspondence between the
divided areas and cache.
Table 3.2
Correspondence between Divided Areas and Cache
Address
Area
Cacheable
Cache Operating
Control
H'00000000 to H'7FFFFFFF
P0
Cacheable
WT bit in CCR1
H'80000000 to H'9FFFFFFF
P1
Cacheable
CB bit in CCR1
H'A0000000 to H'BFFFFFFF
P2
Non cacheable
H'C0000000 to H'DFFFFFFF
P3
Cacheable
WT bit in CCR1
H'E0000000 to H'FFFFFFFF
P4
Non cacheable (internal I/O)



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