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HD6417618 数据表(PDF) 99 Page - Renesas Technology Corp

部件名 HD6417618
功能描述  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

HD6417618 数据表(HTML) 99 Page - Renesas Technology Corp

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Section 5 Exception Handling
Rev. 6.00 Jun. 12, 2007 Page 67 of 610
REJ09B0131-0600
5.1.3
Exception Handling Vector Table
Before exception handling starts, the exception handling vector table must be set in memory. The
exception handling vector table stores the start addresses of exception handling routines. (The
reset exception handling table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets. The
vector table addresses are calculated from these vector numbers and vector table address offsets.
During exception handling, the start addresses of the exception handling routines are fetched from
the exception handling vector table that is indicated by this vector table address.
Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector
table addresses are calculated.
Table 5.3
Vector Numbers and Vector Table Address Offsets
Exception Handling Source
Vector Number
Vector Table Address Offset
Power-on reset
PC
0
H'00000000 to H'00000003
H-UDI reset
SP
1
H'00000004 to H'00000007
(Reserved by system)
2
H'00000008 to H'0000000B
3
H'0000000C to H'0000000F
General illegal instruction
4
H'00000010 to H'00000013
(Reserved by system)
5
H'00000014 to H'00000017
Illegal slot instruction
6
H'00000018 to H'0000001B
(Reserved by system)
7
H'0000001C to H'0000001F
8
H'00000020 to H'00000023
CPU address error
9
H'00000024 to H'00000027
(Reserved by system)
10
H'00000028 to H'0000002B
Interrupt
NMI
11
H'0000002C to H'0000002F
User break
12
H'00000030 to H'00000033
H-UDI
13
H'00000034 to H'00000037
(Reserved by system)
14
H'00000038 to H'0000003B
:
:
31
H'0000007C to H'0000007F



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