HD6417618 datasheet(359/646 Pages) RENESAS

部件名	HD6417618

功能描述	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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359 / 646 page

Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 327 of 610

REJ09B0131-0600

Figure 14.1 shows a block diagram of the SCIF for each channel.

Module data bus

SCFRDR

(16 stage)

SCRSR

RxD

TxD

SCK

CTS

RTS

SCFTDR

(16 stage)

SCTSR

SCSMR

SCLSR

SCFDR

SCFCR

SCFSR

SCBRRn

Parity generation

Parity check

Transmission/

reception

control

Baud rate

generator

Clock

External clock

φ/4

φ/16

φ/64

TXI

RXI

ERI

BRI

SCIF

Internal

data bus

SCSCR

SCSPTR

SCRSR:

SCFRDR:

SCTSR:

SCFTDR:

SCSMR:

SCSCR:

[Legend]

SCFSR:

SCBRR:

SCSPTR:

SCFCR:

SCFDR:

SCLSR:

Receive shift register

Receive FIFO data register

Transmit shift register

Transmit FIFO data register

Serial mode register

Serial control register

Serial status register

Bit rate register

Serial port register

FIFO control register

FIFO data count register

Line status register

Figure 14.1 Block Diagram of SCIF

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