HD6417618 datasheet(421/646 Pages) RENESAS

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Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 389 of 610

REJ09B0131-0600

4. Sending a Break Signal

The I/O condition and level of the TxD pin are determined by the SPBIO and SPBDT bits in

the serial port register (SCSPTR). This feature can be used to send a break signal.

Until TE bit is set to 1 (enabling transmission) after initializing, TxD pin does not work.

During the period, mark status is performed by SPBDT bit. Therefore, the SPBIO and SPBDT

bits should be set to 1 (high level output).

To send a break signal during serial transmission, clear the SPBDT bit to 0 (designating low

level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the

transmitter is initialized regardless of the current transmission state, and 0 is output from the

TxD pin.

5. Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)

The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception,

the SCIF synchronizes internally with the fall of the start bit, which it samples on the base

clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is

shown in figure 14.24.

0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5

16 clocks

8 clocks

Base clock

Receive data

(RxD)

Start bit

–7.5 clocks

+7.5 clocks

Synchronization

sampling timing

Data sampling

timing

Figure 14.24 Receive Data Sampling Timing in Asynchronous Mode

The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.

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