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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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HD6417618 数据表(PDF) 623 Page - Renesas Technology Corp |
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HD6417618 数据表(HTML) 623 Page - Renesas Technology Corp |
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623 / 646 page  Section 21 Electrical Characteristics Rev. 6.00 Jun. 12, 2007 Page 591 of 610 REJ09B0131-0600 21.4.13 Delay Time Variation Due to Load Capacitance (Reference Values) A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 pF) is connected to this LSI's pins is shown below. The graph shown in figure 21.55 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device. If the connected load capacitance exceeds the range shown in figure 21.55, the graph will not be a straight line. +0 +10 +20 +30 +0 +1 +2 +3 +40 +50 Load capacitance (pF) Figure 21.55 Load Capacitance versus Delay Time |
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