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HD6417618 数据表(PDF) 172 Page - Renesas Technology Corp |
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HD6417618 数据表(HTML) 172 Page - Renesas Technology Corp |
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172 / 646 page ![]() Section 7 Bus State Controller (BSC) Rev. 6.00 Jun. 12, 2007 Page 140 of 610 REJ09B0131-0600 7.4.7 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 and RTCNT is cleared to 0. When the RFSH bit in SDCR is 1, a memory refresh request is issued. The request is maintained until the refresh operation is performed. If the request is not processed when the next matching occurs, the previous request is ignored. When the RTCOR is written to, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit Bit Name Initial Value R/W Description 31 to 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 All 0 R/W 8-bit Counter |
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