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HD6417618 数据表(PDF) 236 Page - Renesas Technology Corp |
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HD6417618 数据表(HTML) 236 Page - Renesas Technology Corp |
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236 / 646 page  Section 8 Clock Pulse Generator (CPG) Rev. 6.00 Jun. 12, 2007 Page 204 of 610 REJ09B0131-0600 Notes: 1. Pins MD2 to MD0 should be set during the operation before the mode change or during software standby mode before requesting an interrupt. 2. Clear the STBY bit in STBCR in the exception handling routine for the interrupt in step 6. Otherwise, software standby mode is entered again. For details, see section 10.5.2, Canceling Software Standby Mode. 3. Once bits STC2 to STC0 are changed, the clock is not switched to the specified clock even if only bits PFC2 to PFC0 are changed. When bits STC2 to STC0 are changed after the MDCHG bit has been set to 1, the FRQCR setting must not be made until the clock mode is changed. |
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