HD6417618 datasheet(255/646 Pages) RENESAS

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Section 10 Power-Down Modes

Rev. 6.00 Jun. 12, 2007 Page 223 of 610

REJ09B0131-0600

10.5

Software Standby Mode

10.5.1

Transition to Software Standby Mode

This LSI switches from a program execution state to software standby mode by executing the

SLEEP instruction when the STBY bit in STBCR is 1. In software standby mode, not only the

CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin

also halts.

The contents of the CPU and cache registers remain unchanged. Some registers of on-chip

peripheral modules are, however, initialized. Table 10.3 lists the states of on-chip peripheral

modules registers in software standby mode.

Table 10.3

Module

Registers Initialized

Registers Retaining

Data

Interrupt controller (INTC)



All registers

Clock pulse generator (CPG)



All registers

User break controller (UBC)



All registers

Bus state controller (BSC)



All registers

Ethernet controller (EtherC)



All registers

Direct memory access controller for

Ethernet controller (E-DMAC)



All registers

I/O port



All registers

User debugging interface (H-UDI)



All registers

Serial communication interface with FIFO

(SCIF0 to SCIF2)



All registers

Compare match timer (CMT0 and CMT1)

All registers



Host interface (HIF)



All registers

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