HD6417618 datasheet(315/646 Pages) RENESAS

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Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 283 of 610

REJ09B0131-0600

12.3

Operation

The E-DMAC is connected to the EtherC, and performs efficient transfer of transmit/receive data

between the EtherC and memory (buffers) without the intervention of the CPU. The E-DMAC

itself reads control information, including buffer pointers called descriptors, relating to the buffers.

The E-DMAC reads transmit data from the transmit buffer and writes receive data to the receive

buffer in accordance with this control information. By setting up a number of consecutive

descriptors (a descriptor list), it is possible to execute transmission and reception continuously.

12.3.1

Descriptor List and Data Buffers

Before starting transmission/reception, the communication program creates transmit and receive

descriptor lists in memory. The start addresses of these lists are then set in the transmit and receive

descriptor list start address registers.

The descriptor start address must be aligned so that it matches the address boundary according to

the descriptor length set by the E-DMAC mode register (EDMR). The transmit buffer start address

can be aligned with a byte, a word, and a longword boundary.

(1)

Transmit Descriptor

Figure 12.2 shows the relationship between a transmit descriptor and the transmit buffer.

According to the specification in this descriptor, the relationship between the transmit frame and

transmit buffer can be defined as one frame/one buffer or one frame/multi-buffer.

Transmit descriptor

Transmit buffer

Valid transmit data

TFS26 to TFS0

TD0

TDL

TD1

TBA

Padding (4 bytes)

TD2

31 30 29 28 27 26

Figure 12.2 Relationship between Transmit Descriptor and Transmit Buffer

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