HD6417618 datasheet(327/646 Pages) RENESAS

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Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 295 of 610

REJ09B0131-0600

12.3.4

Multi-Buffer Frame Transmit/Receive Processing

Multi-Buffer Frame Transmit Processing

If an error occurs during multi-buffer frame transmission, the processing shown in figure 12.6 is

carried out by the E-DMAC.

Where the transmit descriptor is shown as inactive (TACT bit = 0) in the figure, buffer data has

already been transmitted normally, and where the transmit descriptor is shown as active (TACT bit

= 1), buffer data has not been transmitted. If a frame transmit error occurs in the first descriptor

part where the transmit descriptor is active (TACT bit = 1), transmission is halted, and the TACT

bit cleared to 0, immediately. The next descriptor is then read, and the position within the transmit

frame is determined on the basis of bits TFP1 and TFP0 (continuing [B'00] or end [B'01]). In the

case of a continuing descriptor, the TACT bit is cleared to 0, only, and the next descriptor is read

immediately. If the descriptor is the final descriptor, not only is the TACT bit cleared to 0, but

write-back is also performed to the TFE and TFS bits at the same time. Data in the buffer is not

transmitted between the occurrence of an error and write-back to the final descriptor. If error

interrupts are enabled in the EtherC/E-DMAC status interrupt permission register (EESIPR), an

interrupt is generated immediately after the final descriptor write-back.

E-DMAC

Inactivates TACT (change 1 to 0)

Descriptor read

Inactivates TACT

Descriptor read

Inactivates TACT

Descriptor read

Inactivates TACT

Descriptor read

Inactivates TACT and writes TFE, TFS

Descriptors

Untransmitted

data is not

transmitted

after error

occurrence

Descriptor is

only processed.

One frame

Buffer

Transmitted data

Untransmitted data

Transmit error

occurrence

Figure 12.6 E-DMAC Operation after Transmit Error

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