AD9520-3SLASHPCBZ datasheet(42/84 Pages) AD

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AD9520-3

Rev. 0 | Page 42 of 84

VCO Calibration

The AD9520 on-chip VCO must be calibrated to ensure proper

operation over process and temperature. The VCO calibration

is controlled by a calibration controller running off a divided

REFIN clock. The calibration requires that the PLL be set up

properly to lock the PLL loop and that the REFIN clock be

present. The REFIN clock must come from a stable source

external to the AD9520.

VCO calibration can be performed two ways: automatically at

power-up and manually. Automatic VCO calibration occurs when

the EEPROM is set to automatically load the preprogrammed

values in the EEPROM, and then automatically calibrate the

VCO. A valid reference must be provided at power-up in order

for the automatic calibration to complete. If this is not the case,

the user must calibrate the VCO manually.

During the first initialization after a power-up or a reset of the

AD9520, a manual VCO calibration sequence is initiated by

setting 0x018[0] = 1b. This can be done as part of the initial

setup before executing update registers (0x232[0] = 1b).

Subsequent to the initial setup, a VCO calibration sequence is

initiated by resetting 0x018[0] = 0b, executing an update registers

operation, setting 0x018[0] = 1b, and executing another update

registers operation. A readback bit (0x01F[6]) indicates when a

VCO calibration is finished by returning a logic true (that is, 1b).

The sequence of operations for the VCO calibration follows:

• Program the PLL registers to the proper values for the PLL loop.

Note that the VCO divider (0x1E0[2:0]) must not be set to static

during VCO calibration.

• For the initial setting of the registers after a power-up or

reset, initiate a VCO calibration by setting 0x018[0] = 1b.

Subsequently, whenever a calibration is desired, set 0x018[0] =

0b, update registers and set 0x018[0] = 1b, update registers.

• A SYNC operation is initiated internally, causing the outputs

to go to a static state determined by normal SYNC function

operation.

• VCO is calibrated to the desired setting for the requested

VCO frequency.

• Internally, the SYNC signal is released, allowing outputs to

continue clocking.

• PLL loop is closed.

• PLL locks.

A SYNC is executed during the VCO calibration; therefore,

the outputs of the AD9520 are held static during the calibration,

which prevents unwanted frequencies from being produced.

However, at the end of a VCO calibration, the outputs may

resume clocking before the PLL loop is completely settled.

The VCO calibration clock divider is set as shown in Table 53

(0x018[2:1]).

The calibration divider divides the PFD frequency (reference

frequency divided by R) down to the calibration clock. The

calibration occurs at the PFD frequency divided by the calibration

divider setting. Lower VCO calibration clock frequencies result in

longer times for a calibration to be completed.

The VCO calibration clock frequency is given by

fCAL_CLOCK = fREFIN/(R × cal_div)

where:

fREFIN is the frequency of the REFIN signal.

R is the value of the R counter.

cal_div is the division set for the VCO calibration divider

(0x018[2:1]).

The user should choose a calibration divider such that the

calibration frequency is less than 6.25 MHz. Table 30 shows the

appropriate value for the calibration divider.

Table 30. VCO Calibration Divider Values for Different

Phase Detector Frequencies

PFD Rate (MHz)

Recommended VCO Calibration Divider

<12

Any

12 to 25

4, 8, 16

25 to 50

8, 16

50 to 100

The VCO calibration takes 4400 calibration clock cycles. Therefore,

the VCO calibration time in PLL reference clock cycles is given by

Time to Calibrate VCO =

4400 × R × cal_div PLL Reference Clock Cycles

The AD9520 does not automatically recalibrate its VCO when

the PLL settings change. This allows for flexibility in deciding

what order to program registers and when to initiate a calibration,

instead of having it happen every time certain PLL registers

have their values change. For example, this allows for the VCO

frequency to be changed by small amounts without having an

automatic calibration occur each time; this should be done with

caution and only when the user knows the VCO control voltage

will not exceed the nominal best performance limits. For example,

a few 100 kHz steps are fine, but a few MHz may not be.

Additionally, because the calibration procedure results in rapid

changes in the VCO frequency, the distribution section is

automatically placed in SYNC until the calibration is finished.

Therefore, this temporary loss of outputs must be expected.

Initiate a VCO calibration under the following conditions:

• After changing any of the PLL R, P, B, and A divider settings,

or after a change in the PLL reference clock frequency. This,

in effect, means any time a PLL register or reference clock is

changed such that a different VCO frequency results.

• Whenever system calibration is desired. The VCO is designed

to operate properly over extremes of temperature even when

it is first calibrated at the opposite extreme. However, a VCO

calibration can be initiated at any time, if desired.

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