AD9520-3SLASHPCBZ datasheet(80/84 Pages) AD

80 / 84 page

AD9520-3

Rev. 0 | Page 80 of 84

Table 57. System

Reg.

Addr

(Hex) Bit(s) Name

Description

230

[3]

Disable power-on SYNC

Power-on SYNC mode. Used to disable the antiruntpulse circuitry.

[3] = 0; enable the antiruntpulse circuitry (default).

[3] = 1; disable the antiruntpulse circuitry.

230

[2]

Power-down SYNC

Powers down the SYNC function.

[2] = 0; normal operation of the SYNC function (default).

[2] = 1; power-down SYNC circuitry.

230

[1]

Power-down distribution reference

Powers down the reference for the distribution section.

[1] = 0; normal operation of the reference for the distribution section (default).

[1] = 1; powers down the reference for the distribution section.

230

[0]

Soft SYNC

The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit

is reversed; that is, a high level forces selected channels into a predetermined static

state, and a 1-to-0 transition triggers a SYNC.

[0] = 0; same as SYNC high.

[0] = 1; same as SYNC low.

Table 58. Update All Registers

Reg.

Addr

(Hex) Bit(s) Name

Description

232

[0]

IO_UPDATE

This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens

on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.

[0] = 1 (self-clearing); update all active registers to the contents of the buffer registers.

Table 59. EEPROM Buffer Segment

Reg.

Addr

(Hex) Bit(s) Name

Description

A00 to

A16

EEPROM Buffer

Segment Register 1

to EEPROM Buffer

Segment Register 23

The EEPROM buffer segment section stores the starting address and number of bytes that are to be

stored and read back to and from the EEPROM. Because the AD9520 register space is noncontiguous,

the EEPROM controller needs to know the starting address and number of bytes in the AD9520 register

space to store and retrieve from the EEPROM. In addition, there are special instructions for the EEPROM

controller, operational codes (that is, IO_UPDATE and end-of-data) that are also stored in the EEPROM

buffer segment. The on-chip default setting of the EEPROM buffer segment registers is designed such

that all registers are transferred to/from the EEPROM, and an IO_UPDATE is issued after transfer. See the

Programming the EEPROM Buffer Segment section for more information.

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