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AD9520-3/PCBZ 数据表(PDF) 46 Page - Analog Devices |
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AD9520-3/PCBZ 数据表(HTML) 46 Page - Analog Devices |
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46 / 84 page  AD9520-3 Rev. 0 | Page 46 of 84 Duty Cycle and Duty-Cycle Correction The duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions: • The M and N values for the channel • DCC enabled/disabled • VCO divider enabled/bypassed • The CLK input duty cycle (note that the internal VCO has a 50% duty cycle) The DCC function is enabled by default for each channel divider. However, the DCC function can be disabled individually for each channel divider by setting the disable divider DCC bit for that channel. Certain M and N values for a channel divider result in a non- 50% duty cycle. A non-50% duty cycle can also result with an even division, if M ≠ N. The duty-cycle correction function automatically corrects non-50% duty cycles at the channel divider output to 50% duty cycle. Duty-cycle correction requires the following channel divider conditions: • An even division must be set as M = N • An odd division must be set as M = N + 1 When not bypassed or corrected by the DCC function, the duty cycle of each channel divider output is the numerical value of (N + 1)/(N + M + 2) expressed as a percent. The duty cycle at the output of the channel divider for various configurations is shown in Table 35 to Table 38. Table 35. Channel Divider Output Duty Cycle with VCO Divider ≠ 1, Input Duty Cycle Is 50% VCO Divider DX Output Duty Cycle N + M + 2 Disable Div DCC = 1 Disable Div DCC = 0 Even Channel divider bypassed 50% 50% Odd = 3 Channel divider bypassed 33.3% 50% Odd = 5 Channel divider bypassed 40% 50% Even, odd Even (N + 1)/(N + M + 2) 50%, requires M = N Even, odd Odd (N + 1)/(N + M + 2) 50%, requires M = N + 1 Table 36. Channel Divider Output Duty Cycle with VCO Divider ≠ 1, Input Duty Cycle Is X% VCO Divider DX Output Duty Cycle N + M + 2 Disable Div DCC = 1 Disable Div DCC = 0 Even Channel divider bypassed 50% 50% Odd = 3 Channel divider bypassed 33.3% (1 + X%)/3 Odd = 5 Channel divider bypassed 40% (2 + X%)/5 Even Even (N + 1)/ (N + M + 2) 50%, requires M = N Even Odd (N + 1)/ (N + M + 2) 50%, requires M = N + 1 Odd = 3 Even (N + 1)/ (N + M + 2) 50%, requires M = N Odd = 3 Odd (N + 1)/ (N + M + 2) (3N + 4 + X%)/(6N + 9), requires M = N + 1 Odd = 5 Even (N + 1)/ (N + M + 2) 50%, requires M = N Odd = 5 Odd (N + 1)/ (N + M + 2) (5N + 7 + X%)/(10N + 15), requires M = N + 1 Table 37. Channel Divider Output Duty Cycle When the VCO Divider Is Enabled and Set to 1 Input Clock Duty Cycle DX Output Duty Cycle N + M + 2 Disable Div DCC = 1 Disable Div DCC = 0 Any Even (N + 1)/ (M + N + 2) 50%, requires M = N 50% Odd (N + 1)/ (M + N + 2) 50%, requires M = N + 1 X% Odd (N + 1)/ (M + N + 2) (N + 1 + X%)/(2 × N + 3), requires M = N + 1 Note that the channel divider must be enabled when VCO divider = 1. Table 38. Channel Divider Output Duty Cycle When the VCO Divider Is Bypassed Input Clock Duty Cycle DX Output Duty Cycle N + M + 2 Disable Div DCC = 1 Disable Div DCC = 0 Any Channel divider bypassed Same as input duty cycle Same as input duty cycle Any Even (N + 1)/ (M + N + 2) 50%, requires M = N 50% Odd (N + 1)/ (M + N + 2) 50%, requires M = N + 1 X% Odd (N + 1)/ (M + N + 2) (N + 1 + X%)/(2 × N + 3), requires M = N + 1 |
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