| 数据搜索系统,热门电子元器件搜索 |
|
MPR083 数据表(PDF) 19 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPR083 数据表(HTML) 19 Page - Freescale Semiconductor, Inc |
|
19 / 35 page ![]() MPR083 Sensors Freescale Semiconductor 19 Preliminary 7 Interrupts 7.1 Introduction The MPR083 has one interrupt output that is configured by registers and alerts the application when a touch or fault is detected. When running in Run2 or Stop2 mode where I2C communication is not available this feature alerts the user to sensor touches. 7.2 Condition for Interrupt There are two cases that latch the Interrupt buffered data available or fault detected. 7.2.1 Buffered Data Available The interrupt for Buffered Data Available will only trigger when the NDF (No Data Flag) transitions from high to low. This signifies that there is new data available in the buffer. The interrupt is deasserted on the first read/write of the FIFO Register and cannot be reasserted for buffered data until the FIFO is empty (either by reading all the data, or clearing the buffer). 7.2.2 Fault Detected The interrupt for a fault detected condition is triggered any time the Fault condition in the Fault Register transitions from zero to non-zero. The interrupt is deasserted when the Fault Register is cleared (by writing to the Fault Register). 7.3 Settings Interrupts are configured through I2C using the Configuration Register (Section 4.7). Two of the settings in this register will affect the interrupt functionality. The Interrupt Enable (IRQEN) must be set high for the IRQ to be enabled. When low, all interrupts will be ignored, and the IRQ pin will never latch. The Interrupt Rate (IRQR) sets the minimum delay between sequential triggered interrupts. The minimum interrupt period can be calculated by taking the product of the (MTP + 5) and IRQR with a factor of 4. Thus, for the minimum setting an interrupt would be triggered no more often than 4 times the master clock. Equation 4 If the MPR083 is using Run2, the minimum interrupt period would be represented by the following equation. Equation 5 7.4 IRQ Pin The IRQ pin is an open-drain, latching interrupt output which requires an external pull-up resistor. The pin will latch down based on the conditions in Section 6.2. The pin will reset when an I2C transmission reads/writes the appropriate register displaying information about the source of the interrupt. Thus if the source is buffered data available then a FIFO Buffer read/write will clear the IRQ pin. If the source is a fault detected then a write of the Fault Register will clear the pin. MinInterruptPeriod ms () MTP 5 + () IRQR × 4 × = MinInterruptPeriod ms () MTP 5 + 8 ---------------------- 1 + ⎝⎠ ⎛⎞ 8 I × RQR 4 × × = |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |