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CS42436 数据表(PDF) 24 Page - Cirrus Logic

部件名 CS42436
功能描述  108 dB, 192 kHz 6-In, 6-Out TDM CODEC
PDF  61 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS42436 数据表(HTML) 24 Page - Cirrus Logic

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DS647F2
CS42436
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL =30pF)
Notes:
23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. For fsck <1 MHz.
Parameter
Symbol
Min
Max
Units
CCLK Clock Frequency
fsck
06.0
MHz
RST Rising Edge to CS Falling
tsrs
20
-
ns
CS Falling to CCLK Edge
tcss
20
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
μs
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 23)
tdh
15
-
ns
CCLK Falling to CDOUT Stable
tpd
-50
ns
Rise Time of CDOUT
tr1
-25
ns
Fall Time of CDOUT
tf1
-25
ns
Rise Time of CCLK and CDIN
(Note 24)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 24)
tf2
-
100
ns
CS
CCLK
CDIN
CDOUT
RST
t
srs
t
scl
t
sch
t
css
t
r2
t
f2
t
csh
t
dsu
t
dh
MSB
MSB
t
pd
Figure 8. Control Port Timing - SPI Format



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