CS42436 datasheet(29/61 Pages) CIRRUS

29 / 61 page

DS647F2

CS42436

5.2.3

Hardware Mode

Single-Ended Mode is selected using a pull-up on the ADC_SDOUT/ADC3_SINGLE pin during startup.

Analog input selection is then made via the AINx_MUX pins. See Tables 3-4 for ADC3 set-up options.

Refer to Figure 10 on page 28 for the internal ADC3 analog input topology.

5.2.4

Software Mode

Single-Ended Mode is selected using the ADC3_SINGLE bit. Analog input selection is then made via the

AINx_MUX bits. See register “ADC Control & DAC De-Emphasis (Address 05h)” on page 44 for all bit se-

lections. Refer to Figure 11 on page 31 for the internal ADC3 analog input topology.

5.2.5

High-Pass Filter and DC Offset Calibration

The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation

filter. If the high-pass filter is disabled during normal operation, the current value of the DC offset for the

corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion re-

sult. This feature makes it possible to perform a system DC offset calibration by:

Running the CS42436 with the high-pass filter enabled until the filter settles. See the Digital Filter

Characteristics for filter settling time.

Disabling the high-pass filter and freezing the stored DC offset.

5.2.5.1

Hardware Mode

The high pass filters for ADC1 and ADC2 are permanently enabled in Hardware Mode.

The high pass

filter for ADC3 is enabled by driving the ADC3_HPF (pin 4) high.

5.2.5.2

Software Mode

The high-pass filter for ADC1/ADC2 can be enabled and disabled.

The high pass filter for ADC3 can

be independently enabled and disabled. The high-pass filters are controlled using the HPF_FREEZE

bit in the register “ADC Control & DAC De-Emphasis (Address 05h)” on page 44.

Configuration Setting

AIN5 Input Selection

ADC_SDOUT

(pin 13)

AIN5_MUX

(pin 1)

47 k

Ω Pull-down

Differential Input (pins 50 & 49)

47 k

Ω Pull-up

Low

AIN5A Input (pin 50)

47 k

Ω Pull-up

High

AIN5B Input (pin 49)

Table 3. AIN5 Analog Input Selection

Configuration Setting

AIN6 Input Selection

ADC_SDOUT

(pin 13)

AIN6_MUX

(pin 2)

47 k

Ω Pull-down

Differential Input (pins 52 & 51)

47 k

Ω Pull-up

Low

AIN5A Input (pin 52)

47 k

Ω Pull-up

High

AIN5B Input (pin 51)

Table 4. AIN6 Analog Input Selection

CS42436 数据表(PDF) 29 Page - Cirrus Logic

CS42436 数据表(HTML) 29 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

数据表下载

链接网址

CS42436 数据表(PDF) 29 Page - Cirrus Logic

CS42436 数据表(HTML) 29 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

数据表 下载

链接网址

数据表下载