CS42436 datasheet(37/61 Pages) CIRRUS

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DS647F2

CS42436

Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown

in Figure 19, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-

dition. The following pseudocode illustrates an aborted write operation followed by a read operation.

Send start condition.

Send 10010xx0 (chip address & write operation).

Receive acknowledge bit.

Send MAP byte, auto increment off.

Receive acknowledge bit.

Send stop condition, aborting write.

Send start condition.

Send 10010xx1(chip address & read operation).

Receive acknowledge bit.

Receive byte, contents of selected register.

Send acknowledge bit.

Send stop condition.

Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each

byte is separated by an acknowledge bit.

5.8

Recommended Power-Up Sequence

5.8.1

Hardware Mode

Hold RST low until the power supply, clocks and hardware control pins are stable. In this state, the

control port is reset to its default settings and VQ will remain low.

Bring RST high. The device will initially be in a low power state with VQ low.

The device will initiate the Hardware Mode power up sequence. All features will default to the

Hardware Mode defaults as listed in Table 2 on page 26 according to the Hardware Mode control

pins. VQ will quick-charge to approximately VA/2 and the analog output bias will clamp to VQ.

Following approximately 2000 sample periods, the device is initialized and ready for normal operation.

Note:

During the Hardware Mode power-up sequence, there must be no transitions on any of the hard-

ware control pins.

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

0 AD1 AD0 0

SDA

0 AD1 AD0 1

CHIP ADDRESS (READ)

START

INCR

12 13 14 15

20 21 22 23 24

26 27 28

10 11

17 18

ACK

DATA + n

STOP

Figure 19. Control Port Timing, I²C Read

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