AT91SAM9261 datasheet(14/43 Pages) ATMEL

14 / 43 page

6062KS–ATARM–15-Jan-09

AT91SAM9261 Preliminary

7.2

Debug and Test Features

• Integrated Embedded In-circuit Emulator Real-Time

– Two real-time Watchpoint Units

– Two Independent Registers: Debug Control Register and Debug Status Register

– Test Access Port Accessible through JTAG Protocol

– Debug Communications Channel

• Debug Unit

–Two-pin UART

– Debug Communication Channel Interrupt Handling

– Chip ID Register

• Embedded Trace Macrocell: ETM9™

– Medium+ Level Implementation

– Half-rate Clock Mode

– Four Pairs of Address Comparators

– Two Data Comparators

– Eight Memory Map Decoder Inputs

– Two 16-bit Counters

– One 3-stage Sequencer

– One 45-byte FIFO

• IEEE1149.1 JTAG Boundary-scan on All Digital Pins

7.3

Bus Matrix

• Five Masters and Five Slaves handled

– Handles Requests from the ARM926EJ-S, USB Host Port, LCD Controller and the

Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD

Controller and USB Host Port.

– Round-Robin Arbitration (three modes supported: no default master, last accessed

default master, fixed default master)

– Burst Breaking with Slot Cycle Limit

• One Address Decoder Provided per Master

– Three different slaves may be assigned to each decoded memory area: one for

internal boot, one for external boot, one after remap.

• Boot Mode Select Option

– Non-volatile Boot Memory can be Internal or External.

– Selection is made by BMS pin sampled at reset.

• Remap Command

– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory

– Allows Handling of Dynamic Exception Vectors

AT91SAM9261 数据表(PDF) 14 Page - ATMEL Corporation

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