AT91SAM9261 datasheet(19/43 Pages) ATMEL

19 / 43 page

6062KS–ATARM–15-Jan-09

AT91SAM9261 Preliminary

The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and

when the user dynamically changes the Internal SRAM configuration, the new 16 Kbyte block

organization may affect the previous configuration from a software point of view.

Table 8-5 illustrates different configurations and the related 16 Kbyte blocks (RB0 to RB9)

assignments.

Note:

1. Configuration after reset.

8.1.1.2

Internal ROM

The AT91SAM9261 integrates a 32 Kbyte Internal ROM mapped at address 0x0040 0000. It is

also accessible at address 0x0 after reset and before remap if the BMS is tied high during reset.

8.1.1.3

USB Host Port

The AT91SAM9261 integrates a USB Host Port Open Host Controller Interface (OHCI). The reg-

isters of this interface are directly accessible on the AHB Bus and are mapped like a standard

internal memory at address 0x0050 0000.

8.1.1.4

LCD Controller

The AT91SAM9261 integrates an LCD Controller. The interface is directly accessible on the

AHB Bus and is mapped like a standard internal memory at address 0x0060 0000.

Table 8-5.

16 Kbyte Block Allocation

Decoded

Area

Address

Configuration Examples and Related 16 Kbyte Block Assignments

ITCM = 0 Kbyte

DTCM = 0 Kbyte

AHB = 160 Kbytes (1)

ITCM = 64 Kbytes

DTCM = 64 Kbytes

AHB = 32 Kbytes

ITCM = 32 Kbytes

DTCM = 64 Kbytes

AHB = 64 Kbytes

ITCM = 32 Kbytes

DTCM = 16 Kbytes

AHB = 112 Kbytes

Internal

SRAM A

(ITCM)

0x0010 0000

RB3

0x0010 4000

RB2

0x0010 8000

RB1

0x0010 C000

RB0

Internal

SRAM B

(DTCM)

0x0020 0000

RB7

0x0020 4000

RB6

0x0020 8000

RB5

0x0020 C000

RB4

Internal

SRAM C

(AHB)

0x0030 0000

RB9

0x0030 4000

RB8

0x0030 8000

RB7

RB1

RB6

0x0030 C000

RB6

RB0

RB5

0x0031 0000

RB5

RB4

0x0031 4000

RB4

RB1

0x0031 8000

RB3

RB0

0x0031 C000

RB2

0x0032 0000

RB1

0x0032 4000

RB0

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