AT91SAM9261 datasheet(29/43 Pages) ATMEL

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6062KS–ATARM–15-Jan-09

AT91SAM9261 Preliminary

10.3

Peripheral Multiplexing on PIO Lines

The AT91SAM9261 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O

lines of the peripheral set.

Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two

peripheral functions, A or B. Table 10-2 on page 31, Table 10-3 on page 32 and Table 10-4 on

page 33 define how the I/O lines of the peripherals A and B are multiplexed on the PIO Control-

lers. The two columns “Function” and “Comments” have been inserted for the user’s own

comments; they may be used to track how pins are defined in an application.

Note that some output only peripheral functions might be duplicated within the tables.

The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral

mode. If I/O is mentioned, the PIO line resets in input with the pull-up enabled, so that the device

is maintained in a static state as soon as the reset is released. As a result, the bit corresponding

to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low.

If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this func-

tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling

memories, in particular the address lines, which require the pin to be driven as soon as the reset

is released. Note that the pull-up resistor is also enabled in this case.

10.3.1

Resource Multiplexing

10.3.1.1

LCD Controller

The LCD Controller can interface with several LCD panels. It supports 4, 8 or 16 bit-per-pixel

without any limitation. Interfacing 24 bit-per-pixel TFTs panel prevents using the SSC0 and the

chip select line 0 of the SPI1.

16 bit-per-pixel TFT panels are interfaced through peripheral B functions, as color data is output

on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on

LCDD2, LCDD10 and LCDD18. Using the peripheral B does not prevent using the SSC0 and

the SPI1 lines.

10.3.1.2

ETM

Using the ETM prevents:

• using the USART1 and USART2 control signals, in particular the SCK lines which are

required to use the USART as ISO7816 and the RTS and CTS to handle hardware

handshaking on the serial lines. In case the ETM and an ISO7816 connection are both

required, the USART0 has to be used as a Smart Card interface.

• using the SSC1

• addressing a static memory of more than 8 Mbytes, which requires the A23 and A24 address

lines

• using the chip select lines 1 to 3 of SPI0 and SPI1

10.3.1.3

EBI

If not required, the NWAIT function (external wait request) can be deactivated by software,

allowing this pin to be used as a PIO.

10.3.1.4

32-bit Data Bus

Using a 32-bit Data Bus prevents:

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