AT91SAM9261 datasheet(34/43 Pages) ATMEL

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6062KS–ATARM–15-Jan-09

AT91SAM9261 Preliminary

10.3.5

System Interrupt

The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:

• the SDRAM Controller

• the Debug Unit

• the Periodic Interval Timer

• the Real-Time Timer

• the Watchdog Timer

• the Reset Controller

• the Power Management Controller

The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used

within the Advanced Interrupt Controller.

10.3.6

External Interrupts

All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to

IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these

peripheral IDs.

10.4

External Bus Interface

• Integrates two External Memory Controllers:

– Static Memory Controller

– SDRAM Controller

• Additional logic for NAND Flash and CompactFlash support

– NAND Flash support: 8-bit as well as 16-bit devices are supported

– CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True

IDE) are supported but the signals -IOIS16 (I/O and True IDE modes) and -ATA SEL

(True IDE mode) are not handled.

• Optimized External Bus

– 16- or 32-bit Data Bus

– Up to 26-bit Address Bus, up to 64 Mbytes addressable

– Eight Chip Selects, each reserved to one of the eight Memory Areas

– Optimized pin multiplexing to reduce latencies on External Memories

• Configurable Chip Select Assignment Managed by EBI_CSA Register located in the MATRIX

user interface

– Static Memory Controller on NCS0

– SDRAM Controller or Static Memory Controller on NCS1

– Static Memory Controller on NCS2

– Static Memory Controller on NCS3, Optional NAND Flash Support

– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash Support

– Static Memory Controller on NCS6 - NCS7

AT91SAM9261 数据表(PDF) 34 Page - ATMEL Corporation

AT91SAM9261 数据表(HTML) 34 Page - ATMEL Corporation

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