CS2300-CP

DS843F1

7

AC ELECTRICAL CHARACTERISTICS

Notes: 4.

PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen-

cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will

5.

6.

7.

In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd

order 100 Hz to 40 kHz bandpass filter.

8.

In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd

order 100 Hz Highpass filter.

9.

Parameters

Symbol

Conditions

Min

Typ

Max

Units

Clock Input Frequency

50 Hz

-

30

MHz

Clock Input Pulse Width

140

10

-

-

-

-

ns

ns

Clock Skipping Timeout

-

-

ms

Clock Skipping Input Frequency

50 Hz

-

80

kHz

PLL Clock Output Frequency

6-

75

MHz

PLL Clock Output Duty Cycle

Measured at VD/2

45

50

55

%

Clock Output Rise Time

20% to 80% of VD

-

1.7

3.0

ns

Clock Output Fall Time

80% to 20% of VD

-

1.7

3.0

ns

Period Jitter

-

35

-

ps rms

Base Band Jitter (100 Hz to 40 kHz)

-

50

-

ps rms

Wide Band JItter (100 Hz Corner)

-

150

-

ps rms

-

-

100

1

200

3

UI

ms