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CS2300-CP 数据表(PDF) 19 Page - Cirrus Logic |
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CS2300-CP 数据表(HTML) 19 Page - Cirrus Logic |
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19 / 32 page ![]() CS2300-CP DS843F1 19 5.4 PLL Clock Output The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the ClkOutDis bit. The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state CLK_OUT may then be unreliable during an unlock condition. Figure 16. PLL Clock Output Options 5.5 Auxiliary Output The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 17, to one of three signals: input clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is con- trolled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is then used to control the output driver type and polarity of the LOCK signal (see section 8.6.2 on page 27). If AUX_OUT is set to CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The driver for the pin can be set to high-impedance using the AuxOutDis bit. Figure 17. Auxiliary Output Selection Referenced Control Register Location ClkOutUnl.............................. “Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 28 ClkOutDis .............................. “PLL Clock Output Disable (ClkOutDis)” on page 25 Referenced Control Register Location AuxOutSrc[1:0]...................... “Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 25 AuxOutDis .............................“Auxiliary Output Disable (AuxOutDis)” on page 24 AuxLockCfg........................... “AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 27 PLL Locked/Unlocked PLL Output 2:1 Mux ClkOutDis 2:1 Mux ClkOutUnl 0 PLL Clock Output Pin (CLK_OUT) 0 1 0 1 PLL Clock Output PLLClkOut 3:1 Mux Auxiliary Output Pin (AUX_OUT) AuxOutDis AuxOutSrc[1:0] AuxLockCfg Frequency Reference Clock (CLK_IN) PLL Clock Output (PLLClkOut) PLL Lock/Unlock Indication (Lock) |
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