数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CS2300-CP 数据表(PDF) 19 Page - Cirrus Logic

部件名 CS2300-CP
功能描述  Fractional-N Clock Multiplier with Internal LCO
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS2300-CP 数据表(HTML) 19 Page - Cirrus Logic

Back Button CS2300-CP_09 Datasheet HTML 15Page - Cirrus Logic CS2300-CP_09 Datasheet HTML 16Page - Cirrus Logic CS2300-CP_09 Datasheet HTML 17Page - Cirrus Logic CS2300-CP_09 Datasheet HTML 18Page - Cirrus Logic CS2300-CP_09 Datasheet HTML 19Page - Cirrus Logic CS2300-CP_09 Datasheet HTML 20Page - Cirrus Logic CS2300-CP_09 Datasheet HTML 21Page - Cirrus Logic CS2300-CP_09 Datasheet HTML 22Page - Cirrus Logic CS2300-CP_09 Datasheet HTML 23Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 19 / 32 page
background image
CS2300-CP
DS843F1
19
5.4
PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the ClkOutDis bit.
The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the
clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state
CLK_OUT may then be unreliable during an unlock condition.
Figure 16. PLL Clock Output Options
5.5
Auxiliary Output
The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 17, to one of three signals: input
clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is con-
trolled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is then used to control
the output driver type and polarity of the LOCK signal (see section 8.6.2 on page 27). If AUX_OUT is set to
CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The
driver for the pin can be set to high-impedance using the AuxOutDis bit.
Figure 17. Auxiliary Output Selection
Referenced Control
Register Location
ClkOutUnl.............................. “Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 28
ClkOutDis .............................. “PLL Clock Output Disable (ClkOutDis)” on page 25
Referenced Control
Register Location
AuxOutSrc[1:0]...................... “Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 25
AuxOutDis .............................“Auxiliary Output Disable (AuxOutDis)” on page 24
AuxLockCfg........................... “AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 27
PLL Locked/Unlocked
PLL Output
2:1 Mux
ClkOutDis
2:1 Mux
ClkOutUnl
0
PLL Clock Output Pin
(CLK_OUT)
0
1
0
1
PLL Clock Output
PLLClkOut
3:1 Mux
Auxiliary Output Pin
(AUX_OUT)
AuxOutDis
AuxOutSrc[1:0]
AuxLockCfg
Frequency Reference Clock
(CLK_IN)
PLL Clock Output
(PLLClkOut)
PLL Lock/Unlock Indication
(Lock)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com