CS2300-CP

14

DS843F1

634 ms) after CLK_IN is removed (see Figure 10). This is true as long as CLK_IN does not glitch or have

an effective change in period as the clock source is removed, otherwise the PLL will interpret this as a

the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See “PLL Clock Out-

put” on page 19. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified

time listed in the “AC Electrical Characteristics” on page 7 after which lock will be acquired and the PLL

output will resume.

the ClkSkipEn bit should be disabled. If it is not disabled, the device will behave as shown in Figure 11;

note that the lower figure shows that the PLL output frequency may change and be incorrect without an

indication of an unlock condition.

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=0

Lock Time

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=1

Lock Time

= invalid clocks

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=0

Lock Time

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=1

Lock Time

= invalid clocks

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn= 1

ClkOutUnl=1

Lock Time

= invalid clocks