CS2300-CP

DS843F1

3

8.6.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 27

8.6.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 27

8.6.3 Enable Device Configuration Registers 3 (EnDevCfg3) ........................................................ 27

8.7 Function Configuration 2 (Address 17h) ........................................................................................ 28

8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 28

8.7.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 28

8.8 Function Configuration 3 (Address 1Eh) ........................................................................................ 28

8.8.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 28

9. CALCULATING THE USER DEFINED RATIO .................................................................................... 29

9.1 High Resolution 12.20 Format ....................................................................................................... 29

9.2 High Multiplication 20.12 Format ................................................................................................... 29

10. PACKAGE DIMENSIONS .................................................................................................................. 30

THERMAL CHARACTERISTICS ......................................................................................................... 30

11. ORDERING INFORMATION .............................................................................................................. 31

12. REFERENCES .................................................................................................................................... 31

13. REVISION HISTORY .......................................................................................................................... 32

LIST OF FIGURES

Figure 1. Typical Connection Diagram ........................................................................................................ 5

Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 8

Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 8

Figure 4. CLK_IN Random Jitter Rejection and Tolerance .........................................................................8

Figure 5. Control Port Timing - I²C Format .................................................................................................. 9

Figure 6. Control Port Timing - SPI Format (Write Only) .......................................................................... 10

Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 11

Figure 8. Hybrid Analog-Digital PLL .......................................................................................................... 12

Figure 9. External Component Requirements for LCO ............................................................................. 13

Figure 10. CLK_IN removed for > 223 LCO cycles ................................................................................... 14

Figure 13. Low bandwidth and new clock domain .................................................................................... 16

Figure 14. High bandwidth with CLK_IN domain re-use ........................................................................... 16

Figure 15. Ratio Feature Summary ........................................................................................................... 18

Figure 16. PLL Clock Output Options ....................................................................................................... 19

Figure 17. Auxiliary Output Selection ........................................................................................................ 19

Figure 18. Control Port Timing in SPI Mode ............................................................................................. 21

Figure 19. Control Port Timing, I²C Write .................................................................................................. 22

Figure 20. Control Port Timing, I²C Aborted Write + Read .......................................................................22

LIST OF TABLES

Table 1. Ratio Modifier .............................................................................................................................. 17

Table 2. Example 12.20 R-Values ............................................................................................................ 29

Table 3. Example 20.12 R-Values ............................................................................................................ 29