ST7263BEX datasheet(68/186 Pages) STMICROELECTRONICS

68 / 186 page

On-chip peripherals

ST7263Bxx

68/186

Doc ID 7516 Rev 8

One Pulse mode

One Pulse mode enables the generation of a pulse when an external event occurs. This

mode is selected via the OPM bit in the CR2 register.

The One Pulse mode uses the input Capture1 function and the output Compare1 function.

Procedure

To use One Pulse mode:

Load the OC1R register with the value corresponding to the length of the pulse (see the

formula in the opposite column).

Select the following in the CR1 register:

–

Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the

pulse.

–

Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the

pulse.

–

Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the

ICAP1 pin must be configured as floating input).

Select the following in the CR2 register:

–

Set the OC1E bit, the OCMP1 pin is then dedicated to the output Compare 1

function.

–

Set the OPM bit.

–

Select the timer clock CC[1:0] (see Table 24).

Figure 37.

One Pulse mode cycle

Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is

loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the

ICIE bit is set.

Clearing the input Capture interrupt request (that is, clearing the ICFi bit) is done in two

steps:

Reading the SR register while the ICFi bit is set.

An access (read or write) to the ICiLR register.

event occurs

Counter

= OC1R

OCMP1 = OLVL1

When

on ICAP1

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

ICR1 = Counter

ST7263BEx 数据表(PDF) 68 Page - STMicroelectronics

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