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ST7263BEx 数据表(PDF) 95 Page - STMicroelectronics |
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ST7263BEx 数据表(HTML) 95 Page - STMicroelectronics |
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95 / 186 page ![]() ST7263Bxx On-chip peripherals Doc ID 7516 Rev 8 95/186 Baud Rate register (SCIBRR) Reset value: 0000 0000 (00h) . 7 0 SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 Read/write [7:6] SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges (see Table 29). [5:3] SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock (see Table 30). [2:0] SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock (see Table 31). Table 29. Prescaling factors PR prescaling factor SCP1 SCP0 10 0 30 1 41 0 13 1 1 Table 30. TR dividing factors TR dividing factor SCT2 SCT1 SCT0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 Table 31. RR dividing factor RR dividing factor SCR2 SCR1 SCR0 1 000 2 001 4 010 |
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