ST7263BEX datasheet(38/186 Pages) STMICROELECTRONICS

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Interrupts

ST7263Bxx

38/186

Doc ID 7516 Rev 8

Peripheral interrupts

Different peripheral interrupt flags in the status register are able to cause an interrupt when

they are active if both:

●

The I bit of the CC register is cleared.

●

The corresponding enable bit is set in the control register.

If any of these two conditions is false, the interrupt is latched and thus remains pending.

Clearing an interrupt request is done by one of the two following operations:

●

Writing “0” to the corresponding bit in the status register.

●

Accessing the status register while the flag is set followed by a read or write of an

associated register.

Note:

The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be

enabled) will therefore be lost if the clear sequence is executed.

All interrupts allow the processor to leave the Wait low power mode.

Exit from Halt mode may only be triggered by an external interrupt on one of the ITi ports

(PA4-PA7 and PB4-PB7), an end suspend mode interrupt coming from USB peripheral, or a

reset.

Figure 19.

Interrupt processing flowchart

BIT I SET

IRET

FROM RESET

LOAD PC FROM INTERRUPT VECTOR

STACK PC, X, A, CC

SET I BIT

FETCH NEXT INSTRUCTION

EXECUTE INSTRUCTION

THIS CLEARS I BIT BY DEFAULT

RESTORE PC, X, A, CC FROM STACK

INTERRUPT

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