ST7263BEX datasheet(73/186 Pages) STMICROELECTRONICS

73 / 186 page

ST7263Bxx

On-chip peripherals

Doc ID 7516 Rev 8

73/186

11.2.7

Each Timer is associated with three control and status registers, and with six pairs of data

registers (16-bit values) relating to the two input captures, the two output compares, the

counter and the alternate counter.

Control register 1 (CR1)

Reset value: 0000 0000 (00h)

ICIE

OCIE

TOIE

FOLV2

FOLV1

OLVL2

IEDG1

OLVL1

Read/write

ICIE input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register

is set.

OCIE output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR

TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.

FOLV2 Forced output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1:Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and

even if there is no successful comparison.

FOLV1 Forced output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if

there is no successful comparison.

OLVL2 output Level 2.

This bit is copied to the OCMP2 pin whenever a successful comparison occurs

with the OC2R register and OCxE is set in the CR2 register. This value is copied

to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode.

IEDG1 input Edge 1.

This bit determines which type of level transition on the ICAP1 pin will trigger the

capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

OLVL1 output Level 1.

The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison

occurs with the OC1R register and the OC1E bit is set in the CR2 register.

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