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ST7263BEx 数据表(PDF) 43 Page - STMicroelectronics

部件名 ST7263BEx
功能描述  Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C
PDF  186 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7263BEx 数据表(HTML) 43 Page - STMicroelectronics

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ST7263Bxx
I/O ports
Doc ID 7516 Rev 8
43/186
9
I/O ports
9.1
Introduction
The I/O ports offer different functional modes:
Transfer of data through digital inputs and outputs and for specific pins
Analog signal input (ADC)
Alternate signal input/output for the on-chip peripherals
External interrupt generation
An I/O port consists of up to 8 pins. Each pin can be programmed independently as a digital
input (with or without interrupt generation) or a digital output.
9.2
Functional description
Each port is associated to 2 main registers:
Data register (DR)
Data Direction register (DDR)
Each I/O pin may be programmed using the corresponding register bits in DDR register: bit
X corresponding to pin X of the port. The same correspondence is used for the DR register.
Input modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Note:
1
All the inputs are triggered by a Schmitt trigger.
2
When switching from input mode to output mode, the DR register should be written first to
output the correct value as soon as the port is configured as an output.
Interrupt function
When an I/O is configured as an input with interrupt, an event on this I/O can generate an
external interrupt request to the CPU. The interrupt sensitivity is given independently
according to the description mentioned in the ITRFRE interrupt register.
Each pin can independently generate an interrupt request.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see interrupts
section). If more than one input pin is selected simultaneously as an interrupt source, this is
logically ORed. For this reason if one of the interrupt pins is tied low, the other ones are
masked.
Table 10.
I/O pin functions
DDR
Mode
0
Input
1
Output



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