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ST7263BEx 数据表(PDF) 12 Page - STMicroelectronics |
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ST7263BEx 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 186 page  Introduction ST7263Bxx 12/186 Doc ID 7516 Rev 8 Figure 1. General block diagram 1. ADC channels: 12 on 48-pin devices (Port B and Port D[3:0]) 8 on 34 and 32-pin devices (Port B) None on 24-pin devices 2. 12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock. 3. The drive from USBVCC is sufficient to only drive an external pull-up in addition to the internal transceiver. 8-BIT CORE ALU OSCIN OSCOUT RESET PORT B 16-BIT TIMER PORT A PORT C PB[7:0] (8 bits) PC[2:0] (3 bits) OSCILLATOR INTERNAL CLOCK CONTROL RAM (1024 Bytes) PA[7:0] (8 bits) VSS VDD POWER SUPPLY SCI PROGRAM (32K Bytes) I²C MEMORY ADC(1) (UART) USB SIE OSC/3 LVD WATCHDOG VSSA VDDA VPP/TEST USB DMA USBDP USBDM USBVCC OSC/4 or OSC/2 for USB2) PORT D PD[7:0] (8 bits) |
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