MCP3421

DS22003E-page 4

© 2009 Microchip Technology Inc.

Gain Error

(Note 5)

—

0.05

0.35

%

PGA = 1, DR = 3.75 SPS

PGA Gain Error Match

(Note 5)

—

0.1

—

%

Between any 2 PGA gains

Gain Error Drift

(Note 5)

—

15

—

ppm/°C

PGA=1, DR=3.75 SPS

Offset Error

—

15

40

µV

Tested at PGA = 1

Offset Drift vs. Temperature

—

50

—

nV/°C

Common-Mode Rejection

—

105

—

dB

at DC and PGA =1,

—

110

—

dB

at DC and PGA =8,

—

5

—

ppm/V

PGA = 1

Power Supply Rejection at DC

—

100

—

dB

PGA = 1

Power Requirements

Voltage Range

2.7

—

5.5

V

Supply Current during

Conversion

—

155

190

µA

—

145

—

µA

Supply Current during Standby

Mode

—0.1

0.5

µA

High level input voltage

V

Low level input voltage

—

—

V

Low level output voltage

——

0.4

V

Hysteresis of Schmitt Trigger

for inputs

(Note 7)

——

V

line is active

——

10

µA

Input Leakage Current

——

1

µA

-1

—

—

µA

Pin capacitance

—

—

10

pF

—

—

400

pF

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for T

Parameters

Sym

Min

Typ

Max

Units

Conditions

Note 1:

Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.

This parameter is ensured by characterization and not 100% tested.

2:

This input impedance is due to 3.2 pF internal input sampling capacitor.

3:

The total conversion speed includes auto-calibration of offset and gain.

4:

INL is the difference between the endpoints line and the measured code at the center of the quantization band.

5:

6:

Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA.

7:

This parameter is ensured by characterization and not 100% tested.

8:

This parameter is ensured by design and not 100% tested.