MCP3421 datasheet(9/42 Pages) MICROCHIP

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DS22003E-page 9

MCP3421

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

3.1

Analog Inputs (VIN+, VIN-)

VIN+ and VIN- are differential signal input pins. The

MCP3421 device accepts a fully differential analog

input signal which is connected on the VIN+ and VIN-

input pins. The differential voltage that is converted is

defined by VIN = (VIN+ - VIN-) where VIN+ is the voltage

applied at the VIN+ pin and VIN- is the voltage applied

at the VIN- pin. The user can also connect VIN

- pin to

VSS for a single-ended operation. See Figure 6-4 for

differential and single-ended connection examples.

The input signal level is amplified by the programmable

gain amplifier (PGA) before the conversion. The

differential input voltage should not exceed an absolute

of (VREF/PGA) for accurate measurement, where VREF

is the internal reference voltage (2.048V) and PGA is

the PGA gain setting. The converter output code will

saturate if the input range exceeds (VREF/PGA).

The absolute voltage range on each of the differential

input pins is from VSS-0.3V to VDD+0.3V. Any voltage

above or below this range will cause leakage currents

through the Electrostatic Discharge (ESD) diodes at

the input pins. This ESD current can cause unexpected

performance of the device. The common mode of the

analog inputs should be chosen such that both the

differential analog input range and the absolute voltage

range on each pin are within the specified operating

range

defined

Section 1.0

“Electrical

Characteristics” and Section 4.0 “Description of

Device Operation”.

See

Section 4.5 “Input Voltage Range” for more

details of the input voltage range.

Figure 3-1 shows the input structure of the device. The

device uses a switched capacitor input stage at the

front end. CPIN is the package pin capacitance and

typically about 4 pF. D1 and D2 are the ESD diodes.

CSAMPLE is the differential input sampling capacitor.

3.2

Supply Voltage (VDD, VSS)

VDD is the power supply pin for the device. This pin

requires an appropriate bypass capacitor of about

0.1 µF (ceramic) to ground. An additional 10 µF

capacitor (tantalum) in parallel is also recommended

to further attenuate high frequency noise present in

some application boards. The supply voltage (VDD)

must be maintained in the 2.7V to 5.5V range for

specified operation.

VSS is the ground pin and the current return path of the

device. The user must connect the VSS pin to a ground

plane through a low impedance connection. If an

analog ground path is available in the application PCB

(printed circuit board), it is highly recommended that

the VSS pin be tied to the analog ground path or

isolated within an analog ground plane of the circuit

board.

3.3

Serial Clock Pin (SCL)

SCL is the serial clock pin of the I2C interface. The

MCP3421 acts only as a slave and the SCL pin

accepts only external serial clocks. The input data

from the Master device is shifted into the SDA pin on

the rising edges of the SCL clock and output from the

MCP3421 occurs at the falling edges of the SCL clock.

The SCL pin is an open-drain N-channel driver.

Therefore, it needs a pull-up resistor from the VDD line

to the SCL pin. Refer to

Section 5.3 “I2C Serial

Communications” for more details of I2C Serial

Interface communication.

MCP3421

Symbol

Description

1VIN+

Positive Differential Analog Input Pin

2VSS

Ground Pin

3SCL

Serial Clock Input Pin of the I2C Interface

4SDA

Bidirectional Serial Data Pin of the I2C Interface

5VDD

Positive Supply Voltage Pin

6VIN-

Negative Differential Analog Input Pin

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