MCP3421

DS22003E-page 16

© 2009 Microchip Technology Inc.

5.2

Configuration Register

The device has an 8-bit wide configuration register to

select for: input channel, conversion mode, conversion

rate, and PGA gain. This register allows the user to

change the operating condition of the device and check

the status of the device operation.

The user can rewrite the configuration byte any time

during the device operation. Register 5-1 shows the

configuration register bits.

REGISTER 5-1:

CONFIGURATION REGISTER

R/W-1

R/W-0

R/W-0

R/W-1

R/W-0

R/W-0

R/W-0

R/W-0

RDY

C1

C0

O/C

S1

S0

G1

G0

1 *

0 *

0 *

1 *

0 *

0 *

0 *

0 *

bit 7

bit 0

* Default Configuration after Power-On Reset

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

RDY: Ready Bit

This bit is the data ready flag. In read mode, this bit indicates if the output register has been updated

with a latest conversion result. In One-Shot Conversion mode, writing this bit to “1” initiates a new

conversion.

Reading RDY bit with the read command:

1

= Output register has not been updated.

0

= Output register has been updated with the latest conversion result.

Writing RDY bit with the write command:

Continuous Conversion mode: No effect

One-Shot Conversion mode:

1

= Initiate a new conversion.

0

= No effect.

bit 6-5

C1-C0: These bits are not effected for the MCP3421.

bit 4

O/C: Conversion Mode Bit

1

= Continuous Conversion Mode

(Default). The device performs data conversions continuously.

0

= One-Shot Conversion Mode. The device performs a single conversion and enters a low power

standby mode until it receives another write or read command.

bit 3-2

S1-S0: Sample Rate Selection Bit

00 =

240 SPS (12 bits)

(Default)

01 =

60 SPS (14 bits)

10 =

15 SPS (16 bits)

11

=

3.75 SPS (18 bits)

bit 1-0

G1-G0: PGA Gain Selection Bits

00 =

x1

(Default)

01 =

x2

10 =

x4

11

=

x8