MCP3422 datasheet(25/58 Pages) MICROCHIP

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DS22088C-page 25

MCP3422/3/4

5.4

General Call

The device acknowledges the general call address

(0x00 in the first byte). The meaning of the general call

address is always specified in the second byte. Refer

to Figure 5-6. The device supports the following three

general calls.

For more information on the general call, or other I2C

modes, please refer to the Phillips I2C specification.

5.4.1

GENERAL CALL RESET

The general call reset occurs if the second byte is

‘00000110’

(06h). At the acknowledgement of this

byte, the device will abort current conversion and

perform the following tasks:

(a) Internal reset similar to a Power-On-Reset (POR).

All configuration and data register bits are reset to

default values.

(b) Latch the logic status of external address selection

pins (Adr0 and Adr1 pins).

5.4.2

GENERAL CALL LATCH (MCP3423

AND MCP3424)

The general call latch occurs if the second byte is

‘00000100’

(04h). The device will latch the logic

status of the external address selection pins (Adr0 and

Adr1 pins), but will not perform a reset.

5.4.3

GENERAL CALL CONVERSION

The general call conversion occurs if the second byte

is ‘00001000’ (08h). All devices on the bus initiate a

conversion simultaneously. When the device receives

this command, the configuration will be set to the One-

Shot Conversion mode and a single conversion will be

performed. The PGA and data rate settings are

unchanged with this general call.

FIGURE 5-6:

General Call Address

Format.

5.5

High-Speed (HS) Mode

The I2C specification requires that a high-speed mode

device must be ‘activated’ to operate in high-speed

mode. This is done by sending a special address byte

of “00001XXX” following the START bit. The “XXX” bits

are unique to the High-Speed (HS) mode Master. This

byte is referred to as the High-Speed (HS) Master

Mode Code (HSMMC). The MCP3422/3/4 devices do

not acknowledge this byte. However, upon receiving

this code, the device switches on its HS mode filters

and communicates up to 3.4 MHz on SDA and SCL

bus lines. The device will switch out of the HS mode on

the next STOP condition.

For more information on the HS mode, or other I2C

modes, please refer to the Philips I2C specification.

5.6

I2C Bus Characteristics

The I2C specification defines the following bus

protocol:

• Data transfer may be initiated only when the bus

is not busy

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition

Accordingly, the following bus conditions have been

defined using Figure 5-7.

5.6.1

BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

5.6.2

START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

5.6.3

STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations can be ended with a STOP condition.

5.6.4

DATA VALID (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition.

LSB

First Byte

ACK

0 A

XX X X XX X

(General Call Address)

Second Byte

Note:

The I2C specification does not allow

‘00000000’

(00h) in the second byte.

START

ACK

STOP

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