MCP3422 datasheet(20/58 Pages) MICROCHIP

20 / 58 page

MCP3422/3/4

DS22088C-page 20

FIGURE 5-1:

Address Byte.

5.3.2

DEVICE ADDRESS BITS (A2, A1, A0)

AND ADDRESS SELECTION PINS

(MCP3423 AND MCP3424)

The MCP3423 and MCP3424 have two external

device address pins (Adr1, Adr0). These pins can be

set to a logic high (or tied to VDD), low (or tied to VSS),

or left floating (not connected to anything, or tied to

VDD/2), These combinations of logic level using the

two pins allow eight possible addresses. Table 5-3

shows the device address depending on the logic

status of the address selection pins.

The device samples the logic status of the Adr0 and

Adr1 pins in the following events:

Device power-up.

General Call Reset

(See Section 5.4 “General Call”).

General Call Latch

(See Section 5.4 “General Call”).

The device samples the logic status (address pins)

during the above events, and latches the values until a

new latch event occurs. During normal operation (after

the address pins are latched), the address pins are

internally disabled from the rests of the internal circuit.

It is recommended to issue a General Call Reset or

General Call Latch command once after the device

has powered up. This will ensure that the device reads

the address pins in a stable condition, and avoid

latching the address bits while the power supply is

ramping up. This might cause inaccurate address pin

detection.

When the address pin is left “floating”:

When the address pin is left “floating”, the address pin

momentarily outputs a short pulse with an amplitude of

about VDD/2 during the latch event. The device also

latches this pin voltage at the same time.

If the “floating” pin is connected to a large parasitic

capacitance (>20 pF) or to a long PCB trace, this short

floating voltage output can be altered. As a result, the

device may not latch the pin correctly.

It is strongly recommended to keep the “floating” pin

pad as short as possible in the customer application

PCB and minimize the parasitic capacitance to the pin

as small as possible (< 20 pF).

Figure 5-2 shows an example of the Latch voltage

output at the address pin when the address pin is left

“floating”. The waveform at the Adr0 pin is captured by

using an oscilloscope probe with 15 pF of capacitance.

The device latches the floating condition immediately

after the General Call Latch command.

FIGURE 5-2:

General Call Latch

Command and Voltage Output at Address Pin

Left “Floating” (MCP3423 and MCP3424).

Start bit

Read/Write bit

Address Byte

R/W ACK

Device Code

Address Bits (Note 1)

Address Byte:

Acknowledge bit

Address

Note

MCP3423 and MCP3424: Configured by

the user. See Table 5-3 for address bit

configurations.

MCP3422: Programmed at the factory

during production.

Float waveform (output)

at address pin

SCL

SDA

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