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MCP3422 数据表(PDF) 28 Page - Microchip Technology |
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MCP3422 数据表(HTML) 28 Page - Microchip Technology |
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28 / 58 page  MCP3422/3/4 DS22088C-page 28 © 2009 Microchip Technology Inc. High Speed Mode (3.4 MHz) Clock frequency fSCL 0— 3.4 MHz Cb = 100 pF 0— 1.7 MHz Cb = 400 pF Clock high time THIGH 60 — — ns Cb = 100 pF, fSCL = 3.4 MHz 120 — — ns Cb = 400 pF, fSCL = 1.7 MHz Clock low time TLOW 160 — — ns Cb = 100 pF, fSCL = 3.4 MHz 320 — — ns Cb = 400 pF, fSCL = 1.7 MHz SCL rise time (Note 1) TR — — 40 ns From VIL to VIH, Cb = 100 pF, fSCL = 3.4 MHz — — 80 ns From VIL to VIH, Cb = 400 pF, fSCL = 1.7 MHz SCL fall time (Note 1) TF — — 40 ns From VIH to VIL, Cb = 100 pF, fSCL = 3.4 MHz — — 80 ns From VIH to VIL, Cb = 400 pF, fSCL = 1.7 MHz SDA rise time (Note 1) TR: DAT — — 80 ns From VIL to VIH, Cb = 100 pF, fSCL = 3.4 MHz — — 160 ns From VIL to VIH, Cb = 400 pF, fSCL = 1.7 MHz SDA fall time (Note 1) TF: DATA — — 80 ns From VIH to VIL, Cb = 100 pF, fSCL = 3.4 MHz — — 160 ns From VIH to VIL, Cb = 400 pF, fSCL = 1.7 MHz Data hold time (Note 4) THD:DAT 0 — 70 ns Cb = 100 pF, fSCL = 3.4 MHz 0 — 150 ns Cb = 400 pF, fSCL = 1.7 MHz Output valid from clock (Notes 2 and 3) TAA — — 150 ns Cb = 100 pF, fSCL = 3.4 MHz — — 310 ns Cb = 400 pF, fSCL = 1.7 MHz START condition hold time THD:STA 160 — — ns After this period, the first clock pulse is generated START (Repeated) condition setup time TSU:STA 160 — — ns Data input setup time TSU:DAT 10 — — ns STOP condition setup time TSU:STO 160 — — ns TABLE 5-4: I2C SERIAL TIMING SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V to +5.0V, VSS = 0V, CHn+ = CHn- = VREF/2. Parameters Sym Min Typ Max Units Conditions Note 1: This parameter is ensured by characterization and not 100% tested. 2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR). 3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this parameter is too long, Clock Low time (TLOW) can be affected. 4: For Data Input: If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. |
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