MPC5643L datasheet(21/98 Pages) FREESCALE

21 / 98 page

Overview

MPC5643L Microcontroller Data Sheet, Rev. 3

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

•

MCKO (message clock out) pin

•

Four or 12 MDO (message data out) pins1

•Two MSEO (message start/end out) pins

•EVTO (event out) pin

— Auxiliary input port

•EVTI (event in) pin

•

Five-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)

— Supports JTAG mode

•

Host processor (e200) development support features

— Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool

to trace reads or writes, or both, to selected internal memory resources.

— Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by providing visibility

of which process ID or operating system task is activated. An ownership trace message is transmitted when a new

process/task is activated, allowing development tools to trace ownership flow.

— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities

(direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires

between the discontinuities. Thus, static code may be traced.

— Watchpoint messaging (WPM) via the auxiliary port

— Watchpoint trigger enable of program and/or data trace messaging

— Data tracing of instruction fetches via private opcodes

1.3.39

IEEE 1149.1 JTAG Controller (JTAGC)

The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic

when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block

is compliant with the IEEE standard.

The JTAG controller provides the following features:

•

IEEE Test Access Port (TAP) interface with five pins:

—TDI

—TMS

—TCK

—TDO

—JCOMP

•

Selectable modes of operation include JTAGC/debug or normal system operation

•

5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

—BYPASS

— IDCODE

—EXTEST

—SAMPLE

— SAMPLE/PRELOAD

•

Three test data registers: a bypass register, a boundary scan register, and a device identification register. The size of

the boundary scan register is parameterized to support a variety of boundary scan chain lengths.

•

TAP controller state machine that controls the operation of the data registers, instruction register and associated

circuitry

1. Four MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package.

MPC5643L 数据表(PDF) 21 Page - Freescale Semiconductor, Inc

MPC5643L 数据表(HTML) 21 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

数据表下载