MPC5643L datasheet(17/98 Pages) FREESCALE

17 / 98 page

Overview

MPC5643L Microcontroller Data Sheet, Rev. 3

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

1.3.29

Serial Peripheral Interface module (DSPI)

The serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the MPC5643L

and external devices.

A DSPI module provides these features:

•

Full duplex, synchronous transfers

•

Master or slave operation

•

Programmable master bit rates

•

Programmable clock polarity and phase

•

End-of-transmission interrupt flag

•

Programmable transfer baud rate

•

Programmable data frames from 4 to 16 bits

•

As many as eight chip select lines available, depending on package and pin multiplexing

•

Four clock and transfer attributes registers

•

Chip select strobe available as alternate function on one of the chip select pins for de-glitching

•

FIFOs for buffering as many as five transfers on the transmit and receive side

•

Queueing operation possible through use of the eDMA

•

General purpose I/O functionality on pins when not used for SPI

1.3.30

FlexPWM

The pulse width modulator module (FlexPWM) contains four PWM channels, each of which is configured to control a single

half-bridge power stage. Two modules are instantiated on the 257 MAPBGA device; on the 144 LQFP package, only one

module is present. Additionally, four fault input channels are provided per FlexPWM module.

This PWM is capable of controlling most motor types, including:

•

AC induction motors (ACIM)

•

Permanent Magnet AC motors (PMAC)

•

Brushless (BLDC) and brush DC motors (BDC)

•

Switched (SRM) and variable reluctance motors (VRM)

•

Stepper motors

A FlexPWM module implements the following features:

•

16 bits of resolution for center, edge aligned, and asymmetrical PWMs

•

Maximum operating frequency as high as 120 MHz

— Clock source not modulated and independent from system clock (generated via auxiliary PLL)

•

Fine granularity control for enhanced resolution of the PWM period

•

PWM outputs can operate as complementary pairs or independent channels

•

Ability to accept signed numbers for PWM generation

•

Independent control of both edges of each PWM output

•

Synchronization to external hardware or other PWM supported

•

Double buffered PWM registers

— Integral reload rates from 1 to 16

— Half cycle reload capability

•

Multiple ADC trigger events can be generated per PWM cycle via hardware

•

Fault inputs can be assigned to control multiple PWM outputs

•

Programmable filters for fault inputs

MPC5643L 数据表(PDF) 17 Page - Freescale Semiconductor, Inc

MPC5643L 数据表(HTML) 17 Page - Freescale Semiconductor, Inc

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