AT45DB321D datasheet(38/57 Pages) ATMEL

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3597N–DFLASH–04/09

AT45DB321D

21.5 Utilizing the RapidS™ Function

To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full

clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is

designed to always clock its data out on the falling edge of the SCK signal and clock data in on

the rising edge of SCK.

For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the fall-

ing edge of SCK, the host controller should wait until the next falling edge of SCK to latch the

data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order

to give the DataFlash a full clock cycle to latch the incoming data in on the next rising edge of

SCK.

Figure 21-1. RapidS Mode

SCK

MOSI

MISO

234567

MOSI = Master Out, Slave In

MISO = Master In, Slave Out

The Master is the host controller and the Slave is the DataFlash

The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.

The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.

Master clocks out first bit of BYTE-MOSI on the rising edge of SCK.

Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK.

Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK.

Last bit of BYTE-MOSI is clocked out from the Master.

Last bit of BYTE-MOSI is clocked into the slave.

Slave clocks out first bit of BYTE-SO.

Master clocks in first bit of BYTE-SO.

Slave clocks out second bit of BYTE-SO.

Master clocks in last bit of BYTE-SO.

BYTE-MOSI

MSB

LSB

BYTE-SO

MSB

LSB

Slave

AT45DB321D 数据表(PDF) 38 Page - ATMEL Corporation

AT45DB321D 数据表(HTML) 38 Page - ATMEL Corporation

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