AT697F datasheet(28/155 Pages) ATMEL

28 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

When a read access to SRAM is performed, a separate output enable signal is provided for each

SRAM bank and it is only asserted when that bank is selected.

Figure 10. SRAM read transaction (0-waitstate)

data1

data2

lead-out

CLK

RAMS*

RAMOE*

SRAM Write Access

Each byte lane has an individual write strobe (RAMWE*) to allow efficient byte and half-word

writes.

Each write access to SRAM consists of three states and between zero and three waitstates. The

three mandatory states are divided in one write setup cycle, one data cycle and one lead-out

cycle.

Figure 11. SRAM write transaction (0-waitstate)

lead-in

data

lead-out

CLK

RAMS*

RWE*

If the external memory use a common write strobe for the full 32-bit data, set the

MCFG2 RMW. This will enable read-modify-write transactions for sub-word writes.

Waitstates

For application using slow SRAM memories, the SRAM controller provides the capability to

insert wait-states during the SRAM accesses. Two types of wait-states can be inserted :

•

Programmed delay, available for bank 0 up to bank 4

•

‘Hardware’ bus delay, available for bank 4 only

Up to three waitstates can be programmed for SRAM accesses. Read and write waitstates can

be individually programmed. Setting the MCFG2 RAMRWS value defines the number of wait-

states to insert during an SRAM read. Setting the MCFG2

RAMWWS value defines the

number of waitstates to insert during an SRAM write.

AT697F 数据表(PDF) 28 Page - ATMEL Corporation

AT697F 数据表(HTML) 28 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载